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1. general description the pcf8537 is a fully featured liquid crystal display (lcd) 1 driver, specifically designed for high-contrast vertical alignment (va) lcd with multiplex rates up to 1:8. it generates the drive signals for any static or multiple xed lcd containing up to eight backplanes, 46 segments, and up to 352 elements. the pcf8537 features an internal charge pump with internal capacitors for on-chip generation of the lcd driving voltage. to ensure an optimal and stable contrast over the full temperature range, the pcf8537 offers a programmable temperature compensation of the lcd supply voltage. the pcf8537 can be easily connected to a microcontroller by either the two-line i 2 c-bus (pcf8537ah) or a three-line bidirectional spi-bus (pcf8537bh). 2. features and benefits ? low-power single-chip l cd controller and driver ? 352 elements allowing to drive: ? up to 44 7-segment alphanumeric characters ? up to 22 14-segment alphanumeric characters ? selectable backplane drive configuration: st atic, 2, 4, 6, or 8 backplane multiplexing ? software programmable internal charge pump for on-chip lcd voltage generation up to 9 v with internal capacitors ? 400 khz i 2 c-bus interface (pcf8537ah) ? 5 mhz spi-bus interface (pcf8537bh) ? programmable temperature compensation of v lcd in four regions ? selectable display bias configuration ? wide range for digital power supply: from 1.8 v to 5.5 v ? wide lcd supply range: from 2.5 v for lo w threshold lcds and up to 9.0 v for high threshold twisted nematic lcds ? display memory bank switching in st atic, duplex, and quadruplex drive modes ? 352-bit ram for display data storage ? programmable frame frequency in the range of 60 hz to 300 hz in steps of 10 hz; factory calibrated ? integrated temperature sensor with temperature readout ? on chip calibration of intern al oscillator frequency and v lcd ? manufactured in silicon gate cmos process pcf8537 industrial lcd driver for multiplex rates up to 1:8 rev. 1 ? 31 may 2012 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 17 .
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 2 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 3. applications ? white goods ? handheld electronics ? battery operated equipment ? machine control systems ? measuring equipment ? information boards ? panels ? consumer ? industrial ? medical and health care 4. ordering information 5. marking table 1. ordering information type number interface type package name description version pcf8537ah/1 i 2 c-bus tqfp64 plastic thin quad flat package; 64 leads; body 10 ? 10 ? 1.0 mm sot357-1 pcf8537bh/1 spi-bus tqfp64 plastic th in quad flat package; 64 leads; body 10 ? 10 ? 1.0 mm sot357-1 table 2. marking codes type number marking code pcf8537ah/1 pcf8537ah pcf8537bh/1 pcf8537bh
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 3 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 6. block diagram fig 1. block diagram of pcf8537ah 013aaa671 lcd voltage selector clock select and timing oscillator power-on reset clk scl sda a0 backplane outputs display control bp0 to bp5 display segment outputs display register output bank select s0 to s43 pcf8537ah lcd bias generator vlcd command decoder write data control vdd1 vdd2 charge pump (voltage multiplier) t1 t2 temperature sensor t3 i 2 c-bus controller data pointer, auto increment display ram s44/bp7 s45/bp6 reset vss v ss
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 4 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 fig 2. block diagram of pcf8537bh 013aaa672 lcd voltage selector clock select and timing oscillator power-on reset clk scl sdio ce backplane outputs display control bp0 to bp5 display segment outputs display register output bank select s0 to s43 pcf8537bh lcd bias generator vlcd command decoder write data control vdd1 vdd2 charge pump (voltage multiplier) t1 t2 temperature sensor t3 spi-bus controller data pointer, auto increment display ram s44/bp7 s45/bp6 reset vss v ss
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 5 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 7. pinning information 7.1 pinning top view. for mechanical details, see figure 62 . top view. for mechanical details, see figure 62 . fig 3. pin configuration for tqfp64 (pcf8537ah) fig 4. pin configuration for tqfp64 (pcf8537bh) pcf8537ah s31 bp3 s30 bp2 s29 bp1 s28 bp0 s27 vlcd s26 vdd2 s25 vdd1 s24 vss s23 t3 s22 clk s21 t2 s20 t1 s19 a0 s18 scl s17 sda s16 s15 s32 s14 s33 s13 s34 s12 s35 s11 s36 s10 s37 s9 s38 s8 s39 s7 s40 s6 s41 s5 s42 s4 s43 s3 s44/bp7 s2 s45/bp6 s1 bp5 s0 bp4 013aaa673 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 reset pcf8537bh s31 bp3 s30 bp2 s29 bp1 s28 bp0 s27 vlcd s26 vdd2 s25 vdd1 s24 vss s23 t3 s22 clk s21 t2 s20 t1 s19 sdio s18 scl s17 s16 s15 s32 s14 s33 s13 s34 s12 s35 s11 s36 s10 s37 s9 s38 s8 s39 s7 s40 s6 s41 s5 s42 s4 s43 s3 s44/bp7 s2 s45/bp6 s1 bp5 s0 bp4 013aaa674 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 reset ce
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 6 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 7.2 pin description [1] v lcd must be equal to or greater than v dd2 . [2] when the internal v lcd generation is used, this pin drives the v lcd voltage. in this case pin vlcd is an output. when the external supply is requested, then pin vlcd is an input and v lcd can be supplied on it. in this case, the internal charge pump must be disabled (see table 8 ). table 3. pin description of pcf8537ah and pcf8537bh pin symbol type description pcf8537ah pcf8537bh 1 to 32 s31 to s0 output lcd segments 33 reset input active low reset input 34 sda input/output i 2 c-bus serial data ce input spi-bus chip enable - active low 35 scl input i 2 c-bus serial clock scl input spi-bus serial clock 36 a0 input i 2 c-bus slave address selection sdio input/output spi-bus serial data 37, 38, 40 t1 to t3 input test pins; must be tied to v ss in applications 39 clk input/output internal o scillator output, external oscillator input 41 vss supply ground supply 42 vdd1 supply supply voltage 1 43 vdd2 supply supply voltage 2 44 vlcd [1] supply lcd supply [2] 45 to 50 bp0 to bp5 output lcd backplanes 51 s45/bp6 output lcd segments for 1:6 multiplex drive mode; lcd backplanes for 1:8 multiplex drive mode 52 s44/bp7 output 53 to 64 s43 to s32 output lcd segments
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 7 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8. functional description the pcf8537 is a versatile peripheral device designed to interface any microcontroller to a wide variety of lcds. it can directly drive any static or multiplexed lcd containing up to 352 elements. 8.1 commands of pcf8537 the commands to control the pcf8537 are defined in ta b l e 4 . any other combinations of operation code bits that are not mentioned in this document can lead to undesired operation modes of pcf8537. [1] for further information about the register selection bit, see table 30 on page 52 . table 4. commands of pcf8537 the bit labeled with - is not implemented. command name rs [1] bits reference 7 6 5 4 3 2 1 0 initialize 0 0 0 1 1 1 0 1 0 section 8.1.1 otp-refresh 0 1 1 0 1 0 0 0 0 section 8.1.2 oscillator-ctrl 0 1 1 0 0 1 1 coe osc section 8.1.3 charge-pump-ctrl 0 1 1 0 0 0 0 cpe cpc section 8.1.4 temp-msr-ctrl 0 1 1 0 0 1 0 tce tme section 8.1.5 temp-comp 0 0 0 0 1 1 sla[2:0] section 8.1.6 0 0 0 1 0 0 slb[2:0] 0 0 0 1 0 1 slc[2:0] 0 0 0 1 1 0 sld[2:0] set-vpr 0 0 1 0 0 vpr[7:4] section 8.1.7 0 0 1 0 1 vpr[3:0] display-enable 0 0 0 1 1 1 0 0 e section 8.1.8 set-mux-mode 0 0 0 0 0 0 m[2:0] section 8.1.9 set-bias-mode 0 1 1 0 0 0 1 b[1:0] section 8.1.10 load-data-pointer 0 1 0 p[5:0] section 8.1.11 frame-frequency 0 0 1 1 f[4:0] section 8.1.12 bank-select 0 0 0 0 0 1 0 ibs obs section 8.1.13 write-ram-data 1 b[7:0] section 8.1.14 temp-read - td[7:0] section 8.1.15 invmode_ctrl 0 1 1 0 1 0 1 lf 0 section 8.1.16 temp-filter 0 1 1 0 1 0 0 1 tfe section 8.1.17
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 8 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.1.1 command: initialize this command generates a chip-wide reset which resets all command values to their default values. after this command is sent, it is possible to send additional commands without the need to re-initialize the interface. the reset takes 100 ns to complete. 8.1.2 command: otp-refresh during production and testing of the device, ea ch ic is calibrated to achieve the specified accuracy of v lcd , the frame frequency, and the temperature measurement. this calibration is performed on eprom cells called one time programmable (otp) cells. the device reads these cells every time at power-on, after a reset, and every time when the initialize command or the otp-refresh command is sent. remark: it is recommended not to enter power-down mode during the otp refresh cycle. 8.1.3 command: oscillator-ctrl the oscillator-ctrl command switches between internal and external oscillator and enables or disables the pin clk. [1] default value. 8.1.3.1 oscillator the internal logic and lcd drive signals of the pcf8537 are timed either by the built-in oscillator or from an external clock. table 5. initialize - initialize command bit description for further information, see section 8.2 on page 17 . bit symbol binary value description 7 to 0 - 00111010 fixed value table 6. otp-refresh - otp-re fresh command bit description bit symbol binary value description 7 to 0 - 11010000 fixed value table 7. oscillator-ctrl - oscillator control command bit description for further information, see section 8.1.3.1 . bit symbol binary value description 7 to 2 - 110011 fixed value 1coe control pin clk 0 [1] clock signal not available on pin clk; pin clk is in 3-state and may be left floating 1 clock signal available on pin clk 0osc oscillator source 0 [1] internal oscillator used 1 external oscillator used; pin clk becomes an input
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 9 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.1.3.2 internal oscillator when the internal oscillator is us ed, it is possible to make the clock signal available on pin clk by using the oscilla tor-ctrl command (see ta b l e 7 ). if this is not intended, the pin clk should be left open. at power-on the signal at pin clk is disabled and pin clk is in 3-state. if the internal charge pump is enabled, then the internal oscillator starts and is used to run the charge pump. an external oscillator ca n still be applied for driving the display waveforms. the duty cycle of the output clock provided on the clk pin is not always 50 : 50. table 17 on page 13 shows the expected duty cycle for each of the chosen frame frequencies. 8.1.3.3 external clock in applications where an external clock mu st be applied to the pcf8537, bit osc (see ta b l e 7 ) must be set logic 1. in this case, pin clk becomes an input. the clk signal is a signal that is fed into the v dd1 domain. therefore it must have an amplitude equal to the v dd1 voltage supplied to the chip and be referenced to v ss . the clock frequency (f clk ) determines the lcd frame frequency. remark: if an external clock is used then this clock signal must alwa ys be supplied to the device. removing the clock can freeze the lcd in a dc state. removal of the clock is possible when following the correct procedures (see figure 11 on page 21 and figure 12 on page 22 ). 8.1.4 command: charge-pump-ctrl the charge-pump-ctrl command enables or disables the internal v lcd generation and controls the charge pump voltage multiplier setting. [1] default value. table 8. charge-pump-ctrl - charge pump control command bit description for further information, see table 11 on page 11 and section 8.4.3 on page 26 . bit symbol binary value description 7 to 2 - 110000 fixed value 1cpe charge pump switch 0 [1] charge pump disabled; no internal v lcd generation; external supply of v lcd 1 charge pump enabled 0cpc charge pump voltage multiplier setting 0 [1] v lcd = 2 ? v dd2 1v lcd = 3 ? v dd2
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 10 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.1.5 command: temp-msr-ctrl the temp-msr-ctrl command enables or disables the temperature measurement block and the temperature compensation of v lcd . [1] default value. 8.1.6 command: temp-comp the temp-comp command allows setting the temperature compensation coefficients for each of the temperature regions sfa to sfd. for further information, see section 8.4.4.2 . [1] default value. table 9. temp-msr-ctrl - temperature measurement control command bit description for further information, see section 8.4.4 on page 28 . bit symbol binary value description 7 to 2 - 110010 fixed value 1tce temperature compensation switch 0 no temperature compensation of v lcd possible 1 [1] temperature compensation of v lcd possible 0tme temperature measurement switch 0 temperature measurement disabled: no temperature readout possible 1 [1] temperature measurement enabled: temperature readout possible table 10. temp-comp - temperature compensation coefficients command for further information, see section 8.4.4 on page 28 . bit symbol binary value description sla 7 to 3 - 00011 fixed value 2 to 0 sla[2:0] 000 [1] to 111 temperature compensation coefficient sla , see table 26 on page 30 slb 7 to 3 - 00100 fixed value 2 to 0 slb[2:0] 000 [1] to 111 temperature compensation coefficient slb , see table 26 on page 30 slc 7 to 3 - 00101 fixed value 2 to 0 slc[2:0] 000 [1] to 111 temperature compensation coefficient slc , see table 26 on page 30 sld 7 to 3 - 00110 fixed value 2 to 0 sld[2:0] 000 [1] to 111 temperature compensation coefficient sld , see table 26 on page 30
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 11 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.1.7 command: set-vpr with these two instructions, it is possible to set the target v lcd voltage for the internal charge pump. [1] default value. [2] vpr[7:0] = 0h results in v prog(lcd) =3v; vpr[7:0] = c8h results in v prog(lcd) =9v. 8.1.8 command: display-enable this command allows switching the display on and off. the possib ility to disable and enable the display allows impl ementation of blinking the entire display under external control. [1] default value. table 11. set-vpr - set vpr command bit description for further information, see section 8.4.2 on page 25 . bit symbol binary value description set-vpr msb 7 to 4 - 0100 fixed value 3 to 0 vpr[7:4] 0000 [1] to 1111 [2] the four most significant bits of vpr[7:0] set-vpr lsb 7 to 4 - 0101 fixed value 3 to 0 vpr[3:0] 0000 [1] to 1111 [2] the four least signifi cant bits of vpr[7:0] table 12. display-enable - display enable command bit description bit symbol binary value description 7 to 1 - 0011100 fixed value 0e 0 [1] display disabled backplane and segment outputs are internally connected to v ss 1 display enabled
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 12 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.1.9 command: set-mux-mode the multiplex drive mode is confi gured with the bits described in ta b l e 1 3 . [1] default value. 8.1.10 command: set-bias-mode the set-bias-mode command allows setting the bias level. [1] not applicable for static drive mode. [2] default value. 8.1.11 command: load-data-pointer the load-data-pointer command defines the display ram address where the following display data will be sent to. table 13. set-mux-mode - set multiplex drive mode comman d bit description for further information, see section 8.4.5 on page 31 . bit symbol binary value description 7 to 3 - 00000 fixed value 2 to 0 m[2:0] 000 [1] 011 101 111 1:8 multiplex drive mode 8 backplanes and 44 segments 110 1:6 multiplex drive mode 6 backplanes and 46 segments 100 1:4 multiplex drive mode 4 backplanes and 44 segments 010 1:2 multiplex drive mode 2 backplanes and 44 segments 001 static drive mode 1 backplane and 44 segments table 14. set-bias-mode - set bias mode command bit description for further information, see section 8.4.5 on page 31 . bit symbol binary value description 7 to 2 - 110001 fixed value 1 to 0 b[1:0] lcd bias configuration [1] 00 [2] 01 1 4 bias 11 1 3 bias 10 1 2 bias table 15. load-data-pointer - load data pointer command bit description for further information, see section 8.8 on page 44 . bit symbol binary value description 7 to 6 - 10 fixed value 5 to 0 p[5:0] 000000 to 101101 ram address 6-bit binary value of 0 to 45
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 13 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.1.12 command: frame-frequency with the frame-frequency command, the frame frequency and the output clock frequency can be configured. [1] nominal frame frequency calculated for the default clock frequency of 9600 hz. [2] duty cycle definition: % high-level time : % low-level time. [3] default value. table 16. frame frequency - frame frequency and output clock frequency command bit description bit symbol binary value description 7 to 5 - 011 fixed value 4 to 0 f[4:0] see ta b l e 1 7 frame frequency values , see ta b l e 1 7 table 17. frame frequency values f[4:0] nominal frame frequency f fr (hz) [1] resultant output clock frequency, f clk(o) (hz) duty cycle (%) [2] 00000 60 2880 20 : 80 00001 70 3360 7 : 93 00010 80 3840 47 : 53 00011 91 4368 40 : 60 00100 100 4800 33 : 67 00101 109 5232 27 : 73 00110 120 5760 20 : 80 00111 129.7 6226 13 : 87 01000 141.2 6778 5 : 95 01001 150 7200 50 : 50 01010 160 7680 47 : 53 01011 171.4 8227 43 : 57 01100 177.8 8534 41 : 59 01101 192 9216 36 : 64 0 1110 [3] 200 9600 33 : 67 01111 208.7 10018 30 : 70 10000 218.2 10474 27 : 73 10001 228.6 10973 23 : 77 10010 240 11520 20 : 80 10011 252.6 12125 16 : 84 10100, 10101 266.7 12802 10 : 90 10110, 10111 282.4 13555 5 : 95 11000 to 11111 300 14 400 50 : 50
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 14 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.1.12.1 timing and frame frequency the timing of the pcf8537 organizes the intern al data flow of the device. this includes the transfer of display data from the display ram to the display segment outputs. the timing also generates the lcd frame frequency. the frame frequency is a fixed division of the internal clock or of the frequency applied to pin clk when an external clock is used. when the internal clock is used, the clock frequency can be programmed by software such that the nominal frame frequency can be chosen in steps of 10 hz in the range of 60 hz to 300 hz (see ta b l e 1 7 ). furthermore the nominal frame frequency is factory-calibrated with an accuracy of 15 %. when the internal clock is enabled at pin clk by using bit coe, the duty ratio of the clock may change when choosing different values for the frame frequency prescaler. ta b l e 1 7 shows the different output duty ratios for each frame frequency prescaler setting. 8.1.13 command: bank-select for the multiplex drive modes 1:4, 1:2, and the static drive mode, it is possible to write data to one area of the ram while displaying from another. these areas are named ram banks. there are two banks, 0 and 1. figure 39 on page 50 and figure 40 on page 50 show the concept. the bank-select command controls where data is written to and where it is displayed from. [1] default value. 8.1.14 command: write-ram-data by setting the rs bit of the control byte to logic 1, all data transferred is interpreted as ram data and placed in the ram in accordance with the current setting of the ram address pointer (see section 8.1.11 on page 12 ). definition of the rs can be found in table 30 on page 52 . remark: after power-on reset (por) the ram content is random and should be brought to a defined status by clearing it (setting it to logic 0). table 18. bank-select - bank select command bit description for further information, see section 8.9 on page 50 . bit symbol binary value description 7 to 2 - 000010 fixed value 1ibs selects ram bank to write to 0 [1] bank 0 1 bank 1 0obs selects ram bank to read from to the lcd 0 [1] bank 0 1 bank 1 table 19. write-ram-data - write ram data command bit description for further information, see section 8.8 on page 44 . bit symbol binary value description 7 to 0 b[7:0] 00000000 to 11111111 writing data byte-wise to the ram
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 15 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.1.15 command: temp-read the temp-read command allows reading out the temperature values measured by the internal temperature sensor. [1] for this command, bit r/w of the i 2 c-bus slave address byte has to be set logic 1 (see table 31 ). 8.1.16 command: invmode_ctrl the invmode_ctrl command allows changing the drive scheme inversion mode. the waveforms used to drive lcd displays inherently produce a dc voltage across the display cell. the pcf8537 compensates for th e dc voltage by inve rting the waveforms on alternate frames or alternate lines. the choice of compensation method is determined with the lf bit. [1] default value. in frame inversion mode, the dc value is co mpensated across two frames and not within one frame. changing the inversion mode to frame inversion reduces the power consumption, therefore it is useful when power consumption is a key point in the application. frame inversion may not be suitable for all applications. the rms voltage across a segment is better defined, however since the switching frequency is reduced there is possibility for flicker to occur. figure 24 on page 34 to figure 30 on page 40 are showing the waveforms in line inversion mode. figure 31 on page 41 shows an example of frame inversion. table 20. temp-read - temperature readout command bit description for further information, see section 8.4.4 on page 28 . bit symbol binary value description 7 to 0 td[7:0] 00000000 to 11111111 digital temperature values [1] table 21. invmode_ctrl - drive scheme inversion command bit description for further information, see section 8.4.6 on page 34 . bit symbol binary value description 7 to 2 - 110101 fixed value 1lf set inversion mode 0 [1] driving scheme a: line inversion mode 1 driving scheme b: frame inversion mode 0 - 0 fixed value
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 16 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.1.17 command: temp-filter [1] default value. table 22. temp-filter - digital temper ature filter command bit description for further information, see section 8.4.4 on page 28 . bit symbol binary value description 7 to 1 - 1101001 fixed value 0tfe digital temperature filter switch 0 [1] digital temperature filter disabled; the unfiltered digital value of td[7:0] is immediately available for the readout and v lcd compensation, see section 8.4.4.1 1 digital temperature filter enabled
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 17 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.2 start-up and shut-down 8.2.1 power-on reset (por) at power-on, the pcf8537 resets to starting conditions as follows: 1. all backplane and segment outputs are set to v ss . 2. selected drive mode is: 1:8 with 1 4 bias. 3. input and output bank selectors are reset. 4. the i 2 c-bus and spi-bus interface are initialized. 5. the data pointer is cleared (set logic 0). 6. the internal oscillator is running; no clock signal is available on pin clk; pin clk is in 3-state. 7. temperature measurement is enabled. 8. temperature filter is disabled. 9. the internal v lcd voltage generation is disabled. the charge pump is switched off. 10. the v lcd temperature compensation is enabled. 11. the display is disabled. the reset state is as shown in ta b l e 2 3 . remark: do not transfer data on the i 2 c-bus or spi-bus for at least 1 ms after a power-on reset to allow the reset action to complete. table 23. reset state reset state of configuration bits shown in the command table format for clarity. the bit labeled with - has an undefined reset state. command name bits 7 6 5 4 3 2 1 0 oscillator-ctrl110011coe = 0osc = 0 charge-pump-ctrl 1 1 0 0 0 0 cpe = 0 cpc = 0 temp-msr-ctrl110010tce = 1 tme = 1 temp-comp00011sla[2:0] = 000 00100slb[2:0] = 000 00101slc[2:0] = 000 00110sld[2:0] = 000 set-vpr 0 1 0 0 vpr[7:4] = 0000 0 1 0 1 vpr[3:0] = 0000 display-enable0011100e = 0 set-mux-mode00000m[2:0] = 000 set-bias-mode 1 1 0 0 0 1 b[1:0] = 00 load-data-pointer 1 0 p[5:0] is undefined frame-frequency 0 1 1 f[4:0] = 01110 bank-select 0 0 0 0 1 0 ibs = 0 obs = 0 invmode_ctrl 1 1 0 1 0 1 lf = 0 - temp-filter 1101001tfe = 0
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 18 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 the first command sent to the device after the power-on event must be the initialize command (see section 8.1.1 ). after por and before enabling the display, the ram content should be brought to a defined status ? by clearing it (setting it all to logic 0) or ? by writing meaningful content (for example, a graphic) otherwise unwanted display artifacts may appear on the display. 8.2.2 reset pin function the reset pin of the pcf8537 resets all the regi sters to their default state. the reset state is given in ta b l e 2 3 . the ram contents remain unchanged. after the reset signal is removed, the pcf8537 will behave in the same ma nner as after por. see section 8.2.1 for details. 8.2.3 recommended start-up sequences this chapter describes how to proceed with the initialization of the chip in different application modes. (1) this time depends on the external capacitor on pin v lcd . for a capacitor of 100 nf a delay of 5 ms to 15 ms is expected. fig 5. recommended start-up sequence when using the internal charge pump and the internal clock signal wait minimum 1 ms start power-on v dd1 and v dd2 at the same time 013aaa632 set vpr register to desired v lcd value set multiplication factor for charge pump and enable it wait till v lcd reaches programmed value (1) write ram content to be displayed and enable the display stop initiate an otp-refresh initialize command
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 19 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 if the display is enabled too soon after the charge pump is enabled, then the v lcd voltage may not have yet stabilized leadin g to an uneven display effect. fig 6. recommended start-up sequence when using an external supplied v lcd and the internal clock signal (1) the external clock signal can be a pplied after the generation of the v lcd voltage as well. (2) this time depends on the external capacitor on pin v lcd . for a capacitor of 100 nf a delay of 5 ms to 15 ms is expected. fig 7. recommended start-up sequence when using the internal charge pump and an external clock signal wait minimum 1 ms start power-on v dd1 , v dd2 and v lcd at the same time initialize command 013aaa633 write ram content to be displayed and enable the display stop initiate an otp-refresh wait minimum 1 ms start power-on v dd1 and v dd2 at the same time initialize command 013aaa634 set vpr register to desired v lcd value wait till v lcd reaches programmed value (1) write ram content to be displayed and enable the display stop apply external clock signal to pin clk; set osc bit logic 1 (1) (2) initiate an otp-refresh set multiplication factor for charge pump and enable it
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 20 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.2.4 recommended sequences to enter power-down mode with the following sequences, the pcf8537 can be set to a state of minimum power consumption, called power-down mode. fig 8. recommended start-up sequence when using an external supplied v lcd and an external clock signal wait minimum 1 ms start initialize command 013aaa635 write ram content to be displayed and enable the display stop apply external clock signal to pin clk; set osc bit logic 1 power-on v dd1 , v dd2 and v lcd at the same time initiate an otp-refresh fig 9. recommended power-down sequence for minimum power-do wn current when using the internal charge pump and the internal clock signal stop genera- tion of v lcd by setting bit cpe logic 0 start disable dis- play by setting bit e logic 0 disable tem- perature mea- surement by setting bit tme logic 0 013aaa636 stop
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 21 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 fig 10. recommended power-down sequence when using an external supplied v lcd and the internal clock signal fig 11. recommended power-down sequence when using the internal charge pump and an external clock signal start disable dis- play by setting bit e logic 0 disable tem- perature mea- surement by setting bit tme logic 0 013aaa637 stop stop genera- tion of v lcd by setting bit cpe logic 0 start disable dis- play by setting bit e logic 0 disable tem- perature mea- surement by setting bit tme logic 0 013aaa638 stop external clock may be switched off bring pin clk to 3-state by setting bit osc and bit coe logic 0
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 22 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 remark: it is necessary to run the power-down sequence before removing the supplies. depending on the application, care must be ta ken that no other signals are present at the chip input or output pins when removing the supplies (see section 10 ). otherwise this may cause unwanted display artifacts. in the case of uncontrolled removal of supply voltages the pcf8537 will not be damaged. remark: static voltages across the liquid crystal display can build up when the external lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd1 or v dd2 ) is off, or the other way around. this may cause unwanted di splay artifacts. to av oid such artifacts, v lcd , v dd1 , and v dd2 must be applied or removed together. remark: a clock signal must always be supplied to the device when the display is active. removing the clock may freeze the lcd in a dc state, which is not suitable for the liquid crystal. it is recommended to first disable the display and afterwards to remove the clock signal. fig 12. recommended power-down sequence for minimum power- down current when using an external supplied v lcd and an external clock signal start disable dis- play by setting bit e logic 0 disable tem- perature mea- surement by setting bit tme logic 0 013aaa639 stop bring pin clk to 3-state by setting bit osc and bit coe logic 0 external clock may be switched off
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 23 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.3 possible display configurations the pcf8537 is a versatile peripheral de vice designed to interface between any microcontroller to a wide variety of lcd segment or dot matrix displays (see figure 13 ). it can directly drive any static or multiplexed lcd containing up to eight backplanes with 44 segments. the display configurations possible with t he pcf8537 depend on the number of active backplane outputs required. a selection of po ssible display configurations is given in ta b l e 2 4 . [1] 7 segment display has 8 elements including the decimal point. [2] 14 segment display has 16 elements including decimal point and accent dot. all of the display configurations in ta b l e 2 4 can be implemented in the typical systems shown in figure 14 (internal v lcd ) and in figure 15 (external v lcd ). fig 13. example of displays suitable for pcf8537 table 24. selection of display configurations number of digits/characters dot matrix/ elements backplanes segments icons 7 segment [1] 14 segment [2] 8 44 352 44 22 352 dots (8 ? 44) 6 46 276 34 17 276 dots (6 ? 46) 4 44 176 22 11 176 dots (4 ? 44) 2 44 88 11 5 88 dots (2 ? 44) 14 44 4524 4 d o t s ( 1 ? 44) 7-segment with dot 14-segment with dot and accent 013aaa312 dot matrix
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 24 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 the host microcontroller maintains the two-line i 2 c-bus communication channel with the pcf8537ah or the three-line spi-bus with the pcf8537bh. the appropriate biasing voltages for the multiplexed lcd waveforms are generated internally. the only other connections required to complete the system are the power supplies (v dd1 , v dd2, v ss , v lcd ), the external capacitors, and the lcd panel selected for the application. the recommended values for external capacitors on v dd1 , v dd2 , and v lcd are of nominal 100 nf value. when using bigger capacitors, especially on the v lcd , the generated ripple will be consequently smaller. however it will take longer for th e internal charge pump to first reach the target v lcd voltage. if v dd1 and v dd2 are connected externally, the capacitors on v dd1 and v dd2 can be replaced by a single capacitor with a nominal value of 220 nf. remark: in case of insufficient decoupling, ripple on v dd1 and v dd2 will create additional v lcd ripple. the ripple on the v lcd can be reduced by making the v ss connection as low-ohmic as possible. excessive ripple on v lcd may cause flicker on the display. v dd1 from 1.8 v to 5.5 v and v dd2 from 2.5 v to 5.5 v. fig 14. typical i 2 c system configuration when using the internal v lcd generation v dd1 from 1.8 v to 5.5 v, v dd2 from 2.5 v to 5.5 v and v lcd from 2.5 v to 9.0 v. fig 15. typical spi system configuration when using an external v lcd host processor/ micro- controller r = t r 2c b sda scl 44 segment drives 8 backplanes lcd panel (up to 352 elements) pcf8537ah t3 v dd1 v ss v ss 013aaa675 v dd2 v lcd v dd2 v dd1 clk n.c. reset t2 t1 a0 host processor/ micro- controller sdio scl 44 segment drives 8 backplanes lcd panel (up to 352 elements) pcf8537bh t3 v dd1 v ss v ss 013aaa676 v lcd v dd2 v dd1 clk n.c. reset t2 t1 ce v lcd
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 25 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.4 lcd supply voltage 8.4.1 external v lcd supply v lcd can be directly supplied to the vlcd pin. in this case, the intern al charge pump must not be enabled otherwise a high current may occur on pin vdd2 and pin vlcd. when v lcd is supplied externally, no in ternal temperature compensation occurs on this voltage even if bit tce is set logic 1 (see section 8.4.4.2 ). the v lcd voltage which is supplied externally will be available at the segments and backplanes of the device through the chosen bias system. also programming vpr[7:0] will have no effect on the v lcd which is externally supplied. 8.4.2 internal v lcd generation v lcd can be generated and controlled on the chip by using software commands. when the internal charge pump is used, the programmed v lcd is available on pin vlcd. the charge pump generates a v lcd of up to 3 ? v dd2 . the charge pump can be enabled or disabled with the cpe bit (see table 8 on page 9 ). with bit cpc, the charge pump multiplier setting can be configured. the final value of v lcd is a combination of the programmed v prog(lcd) value and the output of the temperature compensation block, v offset(lcd) . (1) the system is shown in figure 16 . v lcd v prog lcd ?? v offset lcd ?? + = vpr[7:0] is the binary value of the programmed voltage. vt[7:0] is the binary value of the temperature compensated voltage. its values come from the temperature compensation block and is a two?s complement which has the value 0h at 20 ? c. . the equations for v offset(lcd) , see table 27 on page 31 . fig 16. v lcd generation including temperature compensation 013aaa640 temperature readout -40 0 +80 +20 +50 temperature 0 offset 8 td[7:0] 8 vt[7:0] vpr[7:0] v lcd 0.03 3 sla slb slc sld 8 8 0.03 v prog(lcd) v offset(lcd) v prog lcd ?? vpr 7:0 ?? 0.03 3 + ? =
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 26 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 figure 17 illustrates how v lcd changes with the programmed value of vpr[7:0]. the programmable range of vpr[7:0] is from 0h to ffh. with the upper part of the programmable range, it is possible to achieve more than 9.0 v, but the pcf8537 has a built-in automatic limitation of v lcd at 9.0 v. if v dd2 is higher than 3.0 v, then it is important that vpr[7:0] is set to a value such that the resultant v lcd (including the temperature correction of vt[7:0]) is higher than v dd2 . 8.4.3 charge pump 8.4.3.1 charge pump configuration to obtain the desired v lcd values, the charge pump has to be configured properly. it has to be taken into account that the maximum theoretical values cannot be reached due to internal losses (see section 8.4.3.2 ). so, for example, it is not possible to get a v lcd = 6.0 v with v dd2 = 3.0 v and a charge pump configuration of 2 times v dd2 . in this case, a charge pump configuration of 3 times v dd2 is needed. 8.4.3.2 charge pump driving capability figure 18 and figure 19 are showing the char ge pump driving capability with different settings of v dd2 and charge pump configurations. (1) if v dd2 > 3.0 v then vpr[7:0] must be set so that v lcd ? v dd2 . (2) automatic limitation for v lcd > 9.0 v. fig 17. v lcd programming of pcf8537 (assuming vt[7:0] = 0h) 013aaa661 00 01 02 3 v v lcd vpr[7:0] 03 04 05 06 . . . . . . fd fe ff 0.03 v fc 9 v c8 c9 ca c7 . . . (1) (2) v dd2
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 27 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 (1) vpr[7:0] = 42h. (2) vpr[7:0] = 85h. (3) vpr[7:0] = c6h. t amb =30 ? c; v dd1 =v dd2 =3.3v. remark: for driving the charge pump safely the v lcd and i dd(lcd) values have to be kept below the flat part of the respective graph. charge pump configuration: v lcd =3 ? v dd2 . fig 18. charge pump driving capability with v dd2 =3.3v (1) vpr[7:0] = 42h. (2) vpr[7:0] = 85h. (3) vpr[7:0] = c6h. t amb =30 ? c; v dd1 =v dd2 =5v. remark: for driving the charge pump safely the v lcd and i dd(lcd) values have to be kept below the flat part of the respective graph. a. charge pump configuration: v lcd =2 ? v dd2 013aaa664 0 0.2 0.4 0.6 0.8 1 0 2 4 6 8 10 i dd(lcd) (ma) v lcd (v) (3) (2) (1) 013aaa662 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 i dd(lcd) (ma) v lcd (v) (3) (2) (1)
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 28 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.4.4 temperature measurement and temperature compensation of v lcd 8.4.4.1 temperature readout the pcf8537 has a built-in temperature sensor which provides an 8 bit digital value, td[7:0], of the ambient temperat ure. this value can be read through the interface (see figure 47 on page 56 and figure 51 on page 59 ). the actual temperature is determined from td[7:0] using equation 2 : (2) the measurement needs about 5 ms to complete and is repeated periodically as soon as bit tme is set logic 1 (see table 9 on page 10 ). the time between measurements is linked to the system clock and hence varies with changes in the chosen frame frequency, see ta b l e 2 5 . the temperature sensor can be thought of as analog to digital converter. like all a/d converters, jitter will exist on the lsb of the output value. this is also true of the temperature sensor in the pcf8537. jitter of the lsb of td[7:0] may lead to contrast (1) vpr[7:0] = 42h. (2) vpr[7:0] = 85h. (3) vpr[7:0] = c6h. t amb =30 ? c; v dd1 =v dd2 =5v. remark: for driving the charge pump safely the v lcd and i dd(lcd) values have to be kept below the flat part of the respective graph. b. charge pump configuration: v lcd =3 ? v dd2 fig 19. charge pump driving capability with v dd2 =5.0v 013aaa663 0 0.4 0.8 1.2 1.6 2 0 2 4 6 8 10 i dd(lcd) (ma) v lcd (v) (3) (2) (1) table 25. temperature measurement update rate selected frame frequency temperature measurement update rate 60 hz 3.3 s 200 hz 1 s 300 hz 0.67 s t (c) 0.9375 td 7:0 ?? 40 ? ? =
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 29 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 stepping of the display due to the v lcd voltage is periodically changing between two different target voltages. for this reason, a filter has been implemented to ensure that lsb jitter does not affect the display performance. like any other filtering, the digital temperature filter (see figure 20 ) introduces a certain delay in the measurement of temperature. this be havior is illustrated in figure 21 . this delay may cause undesired effects at start-up when the environment temperature may be different than the reset value of the pcf8537 which is 20 ? c. in this case, it takes up to 30 s until the correct measured temper ature value will be available. a control bit, tfe (see table 22 on page 16 ), is implemented to enable or disable the digital temperature filter. this bit is set logic 0 by defa ult, which means, that the filter is disabled and the unfiltered environment temperature va lue is available to calculate the desired v lcd . fig 20. temperature measurement block with digital temperature filter (1) environment temperature, t1 ( ? c). (2) measured temperature, t2 ( ? c). (3) temperature deviation, ? t=t2 ? t1. fig 21. temperature measurement delay during ramping up-down of the environment temperature temperature measurement block digital temperature filter td[7:0] unfiltered td[7:0] filtered enabled or disabled by bit tfe to the readout register via i 2 c-bus and to the v lcd compensation block 013aaa642 t (s) 0 160 120 80 40 013aaa643 20 30 10 40 50 t (c) 0 (3) (1) (2) 4 8 0 12 16 dt (c) (3) -4
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 30 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.4.4.2 temperature adjustment of the v lcd due to the temperature dependency of the liquid crystal viscosity the lcd controlling voltage v lcd might have to be adjusted at different temperatures to maintain optimal contrast. the temperature behavior of the liquid comes from the lcd manufacturer. the slope has to be set to compensate for the liquid behavior. internal temperature compensation may be enabled via bit tce (see table 9 on page 10 ). the ambient temperature range is split up into four equally sized regions and a different temperature coefficient can be applied to each. each coefficient can be selected from a choice of eight different slopes. each one of these coefficients may be independently selected (see ta b l e 2 6 ). [1] default value. the slope factors imply a linear correction, ho wever the implementation is in steps of 30 mv. table 26. temperature coefficients sla to sld register value corresponding slope factor, sfa to sfd (mv/ ?c) 000 [1] 0 001 ? 4 010 ? 8 011 ? 16 100 ? 40 101 +4 110 +8 111 +16 fig 22. example of segmented temperature coefficients temperature (c) -40 50 -10 013aaa644 td[7:0] 0h 60h 20h v lcd with temperature compensation (v) zero offset at 20 c 79 20 7fh 40h sfc sfa sfd sfb
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 31 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 the offset voltage is calculated according to ta b l e 2 7 . [1] no temperature compensation is possible above 80 ? c. above this value, the system maintains the compensation value from 80 ? c. example : assumed that t amb = ? 8 ? c; sfb= ? 16 mv/ ? c: remark: care must be taken that the ranges of vpr[7:0] and vt[7:0] do not cause clipping and hence undesired resu lts. the device will not permit overflow or underflow and will clamp results to eith er end of the range. 8.4.5 lcd voltage selector the lcd voltage selector co-ordinates the mult iplexing of the lcd in accordance with the selected lcd drive configuration. the operation of the voltage selector is controlled by the set-bias-mode command (see table 14 on page 12 ) and the set-mux-mode command (see table 13 on page 12 ). intermediate lcd biasing voltages are obtained from an internal voltage divider. the biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of v lcd and the resulting discrimination ratios (d), are given in table 28 . discrimination is a term which is defined as the ratio of the one and off rms voltage across a segment. it can be thought of as a measurement of contrast. table 27. calculation of the v lcd offset voltage temperature range v offset(lcd) voltage (mv) t ? ? 40 ?c ? 40 ?c ? t ?? 10 ?c ? 10 ?c < t ? 20 ?c 20 ? c < t ? 50 ?c 50 ? c < t < 80 ?c 80 ?c ? t [1] v offset lcd ?? 30 sfa ? 30 sfb ? + = v offset lcd ?? 10 ? t ? ?? sfa 30 sfb ? + ? = v offset lcd ?? 20 t ? ?? sfb ? = v offset lcd ?? t20 ? ?? sfc ? = v offset lcd ?? t50 ? ?? sfd 30 sfc ? + ? = v offset lcd ?? 30 sfd ? 30 + sfc ? = v offset lcd ?? 20 8 ?? ?? x16 ? ?? 28 16 ? ?? ? 448mv ? ===
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 32 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 [1] determined from equation 5 . [2] determined from equation 4 . [3] in these examples, the discrimination fa ctor and hence the contrast ratios are smaller. the advantage of these lcd drive mod es is a power saving from a reduction of the lcd voltage v lcd . a practical value for v lcd is determined by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10 % contrast. in the static drive mode, a suitable choice is v lcd >3v th . bias is calculated by , where the values for a are a = 1 for 1 2 bias a = 2 for 1 3 bias a = 3 for 1 4 bias the rms on-state voltage (v on(rms) ) for the lcd is calculated with equation 3 (3) where v lcd is the resultant voltage at the lcd segment and where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 4 for 1:4 multiplex n = 6 for 1:6 multiplex n = 8 for 1:8 multiplex the rms off-state voltage (v off(rms) ) for the lcd is calculated with equation 4 : table 28. lcd drive modes: summary of characteristics lcd drive mode number of: lcd bias configuration [1] v lcd [2] backplanes bias levels static 1 2 static 0 1 ? v on(rms) 1:2 multiplex 2 3 1 2 0.354 0.791 2.236 2.828v off(rms) 1:2 multiplex 2 4 1 3 0.333 0.745 2.236 3.0v off(rms) 1:2 multiplex [3] 25 1 4 0.395 0.729 1.845 2.529v off(rms) 1:4 multiplex [3] 43 1 2 0.433 0.661 1.527 2.309v off(rms) 1:4 multiplex 4 4 1 3 0.333 0.577 1.732 3.0v off(rms) 1:4 multiplex [3] 45 1 4 0.331 0.545 1.646 3.024v off(rms) 1:6 multiplex [3] 63 1 2 0.456 0.612 1.341 2.191v off(rms) 1:6 multiplex 6 4 1 3 0.333 0.509 1.527 3.0v off(rms) 1:6 multiplex 6 5 1 4 0.306 0.467 1.527 3.266v off(rms) 1:8 multiplex [3] 83 1 2 0.467 0.586 1.254 2.138v off(rms) 1:8 multiplex [3] 84 1 3 0.333 0.471 1.414 3.0v off(rms) 1:8 multiplex 8 5 1 4 0.293 0.424 1.447 3.411v off(rms) v off rms ?? v lcd ---------------------- - v on rms ?? v lcd ---------------------- d v on rms ?? v off rms ?? ---------------------- - = 1 1a + ------------ - v on rms ?? a 2 2a n ++ n 1a + ?? ? ----------------------------- - v lcd =
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 33 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 (4) discrimination is the ratio of v on(rms) to v off(rms) and is determined from equation 5 : (5) it should be noted that v lcd is sometimes referred as the lcd operating voltage. 8.4.5.1 electro-optical performance suitable values for v on(rms) and v off(rms) are dependent on the lcd liquid used. the rms voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. for any given liquid, there are two threshold values defined. one point is at 10 % relative transmission (at v th(off) ) and the other at 90 % relative transmission (at v th(on) ), see figure 23 . for a good contrast performance, the following rules should be followed: (6) (7) v on(rms) and v off(rms) are properties of the display driver and are affected by the selection of a (see equation 3 ), n (see equation 5 ), and the v lcd voltage. v th(off) and v th(on) are properties of the lcd liquid and can be provided by the module manufacturer. v th(off) is sometimes just named v th . v th(on) is sometimes named saturation voltage v sat . it is important to match the module properties to those of the driver in order to achieve optimum performance. v off rms ?? a 2 2a ? n + n 1a + ?? ? ----------------------------- - v lcd = v on rms ?? v off rms ?? ---------------------- a1 + ?? n 1 ? ?? + a1 ? ?? n 1 ? ?? + ------------------------------------------- - = fig 23. electro-optical characteristic: relative transmission curve of the liquid v on rms ?? v th on ?? ? v off rms ?? v th off ?? ? v rms [v] 100 % 90 % 10 % off segment grey segment on segment v th(off) v th(on) relative transmission 013aaa494
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 34 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.4.6 lcd drive mode waveforms 8.4.6.1 static drive mode the static lcd drive mode is used when a single backplane is provided in the lcd. v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v (sn + 1) (t) ? v bp0 (t). v on(rms) (t) = v lcd . v off(rms) (t) = 0 v. fig 24. static drive mode wave forms (line inversion mode) 013aaa207 v ss v lcd v ss v lcd v ss v lcd v lcd ? v lcd ? v lcd v lcd state 1 0 v bp0 sn sn+1 state 2 0 v (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 1 (on) state 2 (off) t fr
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 35 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.4.6.2 1:2 multiplex drive mode when two backplanes are provided in the lcd, the 1:2 multiplex mode applies. the pcf8537 allows the use of 1 2 bias or 1 3 bias in this mode as shown in figure 25 and figure 26 . v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.791v lcd . v off(rms) (t) = 0.354v lcd . fig 25. waveforms for the 1:2 multiplex drive mode with 1 2 bias (line inversion mode) 013aaa208 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 2 state 1 v ss v lcd v lcd /2 v ss v ss v lcd v lcd v ss v lcd v lcd v lcd 0 v 0 v v lcd /2 v lcd /2 v lcd /2 ? v lcd ? v lcd ? v lcd /2 ? v lcd /2 sn sn+1 t fr
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 36 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.745v lcd . v off(rms) (t) = 0.333v lcd . fig 26. waveforms for the 1:2 multiplex drive mode with 1 3 bias (line inversion mode) 013aaa209 state 1 bp0 (a) waveforms at driver. (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 ? v lcd ? v lcd 0 v v lcd 2v lcd /3 ? 2v lcd /3 v lcd /3 ? v lcd /3 s n s n+1 t fr v ss v lcd 2v lcd /3 v lcd /3
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 37 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.4.6.3 1:4 multiplex drive mode when four backplanes are provided in the lcd, the 1:4 multiplex drive mode applies, as shown in figure 27 . v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.577v lcd . v off(rms) (t) = 0.333v lcd . fig 27. waveforms for the 1:4 multiplex drive mode with 1 3 bias (line inversion mode) 013aaa211 state 1 bp0 (b) resultant waveforms at lcd segment. lcd segments state 2 bp1 state 1 state 2 bp2 (a) waveforms at driver. bp3 sn sn+1 sn+2 sn+3 t fr v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 v ss v lcd 2v lcd /3 v lcd /3 0 v v lcd 2v lcd /3 -2v lcd /3 v lcd /3 -v lcd /3 -v lcd 0 v v lcd 2v lcd /3 -2v lcd /3 v lcd /3 -v lcd /3 -v lcd v ss v lcd 2v lcd /3 v lcd /3
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 38 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.4.6.4 1:6 multiplex drive mode when six backplanes are provided in the lcd, the 1:6 multiplex driv e mode applies. the pcf8537 allows the use of 1 3 bias or 1 4 bias in this mode as shown in figure 28 and figure 29 . v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.509v lcd . v off(rms) (t) = 0.333v lcd . fig 28. waveforms for 1:6 multiplex drive mode with 1 3 bias (line inversion mode) 001aal399 state 1 state 2 lcd segments t fr v lcd bp0 2v lcd / 3 v lcd / 3 v ss v lcd bp1 2v lcd / 3 v lcd / 3 v ss v lcd bp2 2v lcd / 3 v lcd / 3 v ss v lcd bp3 2v lcd / 3 v lcd / 3 v ss v lcd bp4 2v lcd / 3 v lcd / 3 v ss v lcd bp5 2v lcd / 3 v lcd / 3 v ss v lcd sn (a) waveforms at driver (b) resultant waveforms at lcd segment 2v lcd / 3 v lcd / 3 v ss v lcd sn + 1 2v lcd / 3 v lcd / 3 v ss v lcd state 1 2v lcd / 3 v lcd / 3 v ss v lcd state 2 -v lcd 2v lcd / 3 -2v lcd / 3 v lcd / 3 -v lcd / 3 -v lcd -2v lcd / 3 -v lcd / 3 v ss
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 39 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.467v lcd . v off(rms) (t) = 0.306v lcd . fig 29. waveforms for 1:6 multiplex drive mode with 1 4 bias (line inversion mode) 001aal400 state 1 state 2 lcd segments v lcd 3v lcd / 4 v lcd / 4 v ss bp0 v lcd 3v lcd / 4 v lcd / 4 v ss bp1 v lcd 3v lcd / 4 v lcd / 4 v ss bp2 v lcd 3v lcd / 4 v lcd / 4 v ss bp3 v lcd 3v lcd / 4 v lcd / 4 v ss bp4 v lcd 3v lcd / 4 v lcd / 4 v ss bp5 v lcd -v lcd 3v lcd / 4 -3v lcd / 4 v lcd / 4 -v lcd / 4 v lcd / 2 -v lcd / 2 v ss v lcd v lcd / 2 v ss v lcd v lcd / 2 v ss state 2 v lcd -v lcd 3v lcd / 4 -3v lcd / 4 v lcd / 4 -v lcd / 4 v ss state 1 sn + 1 sn t fr (a) waveforms at driver (b) resultant waveforms at lcd segment
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 40 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.4.6.5 1:8 multiplex drive mode v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.424v lcd . v off(rms) (t) = 0.293v lcd . fig 30. waveforms for 1:8 multiplex drive mode with 1 4 bias (line inversion mode) 001aal398 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 sn sn + 1 state 1 state 2 v lcd 3v lcd / 4 state 1 state 2 lcd segments -v lcd v lcd / 2 v lcd / 4 v ss -v lcd / 4 -v lcd / 2 -3v lcd / 4 -v lcd -3v lcd / 4 -v lcd / 4 v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 2 v lcd v ss v lcd / 2 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss 3 lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd v ss v lcd / 4 3v lcd / 4 v lcd t fr (a) waveforms at driver (b) resultant waveforms at lcd segment
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 41 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 v state1 (t) = v sn (t) ? v bp0 (t). v state2 (t) = v sn (t) ? v bp1 (t). v on(rms) (t) = 0.424v lcd . v off(rms) (t) = 0.293v lcd . fig 31. waveforms for 1:8 multiplex drive mode with 1 4 bias (frame inversion mode) 001aam359 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 sn sn + 1 state 1 state 2 state 1 t fr t fr frame n frame n+1 state 2 lcd segments v lcd 3/4 v lcd 1/4 v lcd v ss 1/4 v lcd 3/4 v lcd 1/2 v lcd 1/2 v lcd v lcd v lcd 3/4 v lcd 1/4 v lcd v ss 1/4 v lcd 3/4 v lcd 1/2 v lcd 1/2 v lcd v lcd v ss 1/2 v lcd v lcd v ss 1/2 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd v ss 1/4 v lcd 3/4 v lcd v lcd (a) waveforms at driver (b) resultant waveforms at lcd segment
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 42 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.5 backplane and segment outputs 8.5.1 backplane outputs the lcd drive section includes eight back plane outputs: bp0 to bp7. the backplane output signals are generated based on t he selected lcd mult iplex drive mode. ta b l e 2 9 describes which outputs are active for each of the multiplex drive modes and what signal is generated. [1] these pins may optionally or alte rnatively be connected to the display to improve drive strength. connect only with the corresponding output pin carrying the sa me signal. if not required, they can be left open circuit. 8.5.1.1 1:8 multiplex drive mode in 1:8 multiplex drive mode, bp0 to bp7 must be connected directly to the lcd. 8.5.1.2 1:6 multiplex drive mode 1:6 multiplex mode is a special case. in this mode bp0 to bp5 must be connected directly to the display as back plane signals and s44 and s45 must be connected to the display as segment signals. 8.5.1.3 1:4 multiplex drive mode in the 1:4 multiplex drive mode, bp0 to bp3 must be connected directly to the lcd. the unused bps may be left open-circuit. optionally they may also be connected to the display to increase drive strength. ? bp0 is repeated on bp4 ? bp1 is repeated on bp5 ? bp2 is repeated on bp6 ? bp3 is repeated on bp7 8.5.1.4 1:2 multiplex drive mode in the 1:2 multiplex drive mode, bp0 and bp1 must be connected directly to the lcd. the unused bps may be left open-circuit. optionally they may also be connected to the display to increase drive strength. ? bp0 is repeated on bp2, bp4, and bp6 ? bp1 is repeated on bp3, bp5, and bp7 table 29. mapping of output pins and corresponding signals with respect to driving mode mux mode output pin bp0 bp1 bp2 bp3 bp4 bp5 s45/bp6 s44/bp7 signal 1:8 bp0 bp1 bp2 bp3 bp4 bp5 bp6 bp7 1:6 bp0 bp1 bp2 bp3 bp4 bp5 s45 s44 1:4 bp0 bp1 bp2 bp3 bp0 [1] bp1 [1] bp2 [1] bp3 [1] 1:2 bp0 bp1 bp0 [1] bp1 [1] bp0 [1] bp1 [1] bp0 [1] bp1 [1] static bp0 bp0 [1] bp0 [1] bp0 [1] bp0 [1] bp0 [1] bp0 [1] bp0 [1]
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 43 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.5.1.5 static drive mode in the static drive mode, bp0 must be connected directly to the lcd. in the static drive mode, the same signal is carried by all eight backplane outputs and they can be connected in parallel for very high drive requirements. ? bp0 is repeated on bp1, bp2, bp3, bp4, bp5, bp6, and bp7 8.5.2 segment outputs the lcd drive section includes up to 46 segment outputs. segments s0 to s43 are always segment outputs. there are also two more segment outputs which become active in 1:6 multiplex mode. these are s45/bp6 and s44/bp7 and must also be connected directly to the display. the segment output signals are generated bas ed on the multiplexed backplane signals and with data resident in the display register. when less than 46 segment outputs are required, the unused segment outputs must be left open-circuit. 8.5.2.1 static, 1:8, 1:4, 1:2 multiplex drive mode in these drive modes, segments s0 to s43 must be connected to the display. 8.5.2.2 1:6 multiplex drive mode in this drive mode, segments s0 to s43, s44, and s45 must be connected to the display.
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 44 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.6 display controller the display controller executes the commands identified by the command decoder. it contains the status registers of the pcf8537 and co-ordinates their effects. the controller is also responsible for loadin g display data into the displa y ram as required by the filling order. 8.7 display register the display register holds the display data while the corresponding multiplex signals are generated. 8.8 display ram the display ram stores lcd data. depending on the multiplex drive mode, the arrangement of the ram is changed. ? multiplex drive mode 1:8: ram is 44 ? 8bit ? multiplex drive mode 1:6: ram is 46 ? 6bit ? multiplex drive mode 1:4: ram is 44 ? 4 bit arranged in two banks ? multiplex drive mode 1:2: ram is 44 ? 2 bit arranged in two banks ? static drive mode: ram is 44 ? 1 bit arranged in two banks a logic 1 in the ram bit map indicates the on-state of the corresponding lcd element; similarly, a logic 0 indicates the off-state. there is a one-to-one correspondence between ? the bits in the ram bitmap and the lcd elements, ? the ram columns and the segment outputs, ? the ram rows and the backplane outputs.
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 45 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 the display ram bitmap shows the direct relationship between the display ram column and the segment outputs; and between the bits in a ram row and the backplane outputs. fig 32. display ram bitmap s0 s1 s2 s3 s4 s5 s6 s7 s38 s39 s40 s41 s42 s43 row0/bp0 row1/bp1 row2/bp2 row3/bp3 row4/bp4 row5/bp5 row6/bp6 row7/bp7 s0 s1 s2 s3 s4 s5 s6 s7 s38 s39 s40 s41 s42 s43 s44 s45 row0/bp0 row1/bp1 row2/bp2 row3/bp3 row4/bp4 row5/bp5 s0 s1 s2 s3 s4 s5 s6 s7 s38 s39 s40 s41 s42 s43 row0/bp0 row1/bp1 row2/bp2 row3/bp3 row4/bp0 row5/bp1 row6/bp2 row7/bp3 s0 s1 s2 s3 s4 s5 s6 s7 s38 s39 s40 s41 s42 s43 row0/bp0 row1/bp1 row2 row3 row4/bp0 row5/bp1 row6 row7 s0 s1 s2 s3 s4 s5 s6 s7 s38 s39 s40 s41 s42 s43 row0/bp0 row1 row2 row3 row4/bp1 row5 row6 row7 bank 0 bank 1 bank 0 bank 1 bank 0 bank 1 display ram addresses (columns)/segment outputs (s) display ram bits (rows)backplane outputs (bp) multiplex drive mode 1:8 multiplex drive mode 1:6 multiplex drive mode 1:4 multiplex drive mode 1:2 static drive mode 013aaa645
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 46 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 the display ram bit map, figure 32 , shows row 0 to row 7 which correspond with the backplane outputs bp0 to bp7, and column 0 to column 45 which correspond with the segment outputs s0 to s45. in multiplexed lcd applications, the data of each row of the display ram is time-multiplexed with the corresponding backplane (row 0 with bp0, row 1 with bp1, and so on). when display data is transmitted to the pcf8537, the display bytes received are stored in the display ram in accordance with the select ed lcd multiplex drive mode. the data is stored as it arrives. depending on the cu rrent multiplex drive mode, data is stored singularly, in pairs, quadruples, sextuples or bytes. 8.8.1 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequen ce commences with the initialization of the data pointer by the load-data-pointer command (see table 15 on page 12 ). following this command, an arriving data byte is stored starting at the display ram address indicated by the data pointer. after each byte stored , the data pointer is automatically incremented in accordance with the chosen lcd mu ltiplex drive mode configuration: ? by eight (static drive mode) ? by four (1:2 multiplex drive mode) ? by two (1:4 multiplex drive mode) ? by one or two (1:6 multiplex drive mode), see figure 37 on page 49 ? by one (1:8 mult iplex drive mode) when the address counter reaches the end of the ram row, it stops incrementing after the last byte is transmitted. redundant bits of the last byte transmitted are discarded. additional bytes, sent after the end of the ram is reached, will be di scarded too. the data pointer does not wrap around to the beginning. to send new ram data, the data pointer must be reset. if an i 2 c-bus or spi-bus data access is terminated early, then the state of the data pointer is unknown. the data pointer must then be re-written before further ram accesses.
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 47 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.8.2 ram filling in static drive mode in the static drive mode the eight transmitte d data bits are placed in eight successive display ram columns in row 0 (see figure 33 ). in order to fill the whole ram row, 6 bytes must be sent to the pcf85 37, but the last 4 bits from the last byte are discarded (see figure 34 ). when bit ibs is set to bank 1 (see table 18 on page 14 ), then data is stored in row 4. 8.8.3 ram filling in 1:2 multiplex drive mode in the 1:2 multiplex drive mode the eight tr ansmitted data bits are placed in four successive display ram columns (see figure 35 ). in order to fill the whole two ram rows 11 bytes need to be sent to the pcf8537. fig 33. display ram filling order in static drive mode fig 34. discarded bits at the end of data transmission 0 1 2 3 4 5 6 7 39 40 41 42 43 b0 b1b2b3b4b5b6 b7 0 msb lsb transmitted data byte display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa646 b0 b1 b2 b3b4 b5 b6 b7 01234567 3233343536 display ram data pointer 37 38 39 40 41 42 43 0 a7 a6 a5 a4 a3 a2 a1 a0 e7 e6 e5 e4 e3 e2 e1 e0 f7 f6 f5 f4 f3 f2 f1 f0 discarded 013aaa647 fig 35. display ram filling orde r in 1:2 multiplex drive mode 012 34 56 7 3940414243 b0b1b2b3 b4 b5 b6 b7 0 1 b7 b6 b5 b4 b3 b2 b1 b0 lsb msb transmitted data byte 013aaa648 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 48 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 when bit ibs is set to bank 1 (see table 18 on page 14 ), then data is stored in row 4 and row 5. 8.8.4 ram filling in 1:4 multiplex drive mode in the 1:4 multiplex drive mode the eight transmitted data bits are placed in two successive display ram colu mns of four rows (see figure 36 ). in order to fill the whole four ram rows 22 bytes need to be sent to the pcf8537. when bit ibs is set to bank 1 (see table 18 on page 14 ), then data is stored in rows 4 to row 7. 8.8.5 ram filling in 1:6 multiplex drive mode in the 1:6 multiplex drive mode the ram is organized in six rows and 46 columns. the eight transmitted data bits are placed in su ch a way, that a colu mn is filled up (see figure 37 ). the remaining bits are wrapped up into the next column. in order to fill the whole ram addresses 35 bytes need to be sent to the pcf8537, however the four least significant bits of the 35th byte are discarded. fig 36. display ram filling orde r in 1:4 multiplex drive mode 012 34 56 7 3940414243 b0 b1b2 b3 b4b5 b6 b7 0 msb lsb 1 2 3 transmitted data byte b7 b6 b5 b4 b3 b2 b1 b0 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa649
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 49 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 when data transfer is initiated, then the msb of the first byte will always be placed in row 0. data must be transfer red contiguously to achieve ram filling as described in figure 37 . 8.8.6 ram filling in 1:8 multiplex drive mode in the 1:8 multiplex drive mode the eight transmi tted data bits are placed into eight rows of one display ram column (see figure 38 ). in order to fill the whole ram addresses 44 bytes need to be sent to the pcf8537. fig 37. display ram filling orde r in 1:6 multiplex drive mode 0 1 2 3 4 5 6 7 4142434445 a0 a1a2a3a4a5a6a7 0 msb lsb 1 2 3 4 5 transmitted data bytes a7 a6 a5 a4 a3 a2 a1 a0 b0b1 b2 b3 b4b5b6 c0c1c2c3c4c5c6 b7 c7 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa650 data pointer incrementation h7 h6 h5 h4 h3 h2 h1 h0 discarded fig 38. display ram filling orde r in 1:8 multiplex drive mode 0 1 2 3 4 5 6 7 39 40 41 42 43 b0 b1b2b3b4b5b6 b7 0 msb lsb 1 2 3 4 5 6 7 transmitted data byte b7 b6 b5 b4 b3 b2 b1 b0 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa651
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 50 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.9 bank selection the pcf8537 includes a ram bank switching fe ature in the static, 1:2, and 1:4 multiplex drive modes. a bank can be thought of as a collection of ram rows. the ram bank switching gives the provision for preparing di splay information in an alternative bank and to be able to switch to it once it is complete. there are two banks; bank 0 and bank 1. figure 32 on page 45 shows the location of these banks relative to the ram map. input and output banks can be set independently from one another with the bank-select command (see table 18 on page 14 ). figure 39 shows the concept. in figure 40 an example is shown for 1:4 multiplex drive mode where the displayed data is read from the first four rows of the memory (b ank 0), while the transmit ted data is stored in the second four rows of the memory (bank 1). 8.9.1 input bank selection the ibs (input bank selection) bit of the bank-select command (see ta b l e 1 8 ) controls where display data is loa ded into the display ram. the input bank selection works indep endently of output bank selection. fig 39. bank selection fig 40. example of the bank-select comm and with multiplex drive mode 1:4 microcontroller display ram bank 0 bank 1 013aaa423 ibs controls the input data path obs controls the output data path 4 5 6 7 display ram columns/segment outputs (s) columns display ram rows/ backplane outputs (bp) rows 013aaa652 012 34 56 7 3940414243 0 1 2 3 to the lcd output ram bank input ram bank to the ram
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 51 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 8.9.2 output bank selection the obs bit of the bank-select command (see table 18 on page 14 ) controls from which bank display data is taken, the output bank selection works independently of input bank selection.
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 52 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 9. bus interfaces 9.1 control byte after initiating the communication over the bus and sending the slave address (i 2 c-bus, see section 9.2 ) or subaddress (spi-bus, see section 9.3 ), a control byte follows. the purpose of this byte is to indicate both, the content for the following data bytes (ram or command) and to indica te that more control bytes will follow. typical sequences could be: ? slave address/subaddress - control byte - command byte - command byte - command byte - end ? slave address/subaddress - control byte - ram byte - ram byte - ram byte - end ? slave address/subaddress - control byte - command byte - control byte - ram byte - end in this way, it is possible to send a mixt ure of ram and command data in one access or alternatively, to send just one type of data in one access. table 30. control byte description bit symbol binary value description 7co continue bit 0 last control byte 1 control bytes continue 6rs register selection 0 command register 1 data register 5 to 0 - not relevant fig 41. control byte format mgl753 not relevant co 76 543210 rs msb lsb
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 53 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 9.2 i 2 c-bus interface char acteristics (pcf8537ah) the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 9.2.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 42 ). 9.2.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low change of the data line, while the clock is high is defined as the start condition (s). a low-to-high change of the data line while th e clock is high is defined as the stop condition (p). the start and stop conditions are shown in figure 43 . 9.2.3 system configuration a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. the system configuration is shown in figure 44 . fig 42. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 43. definition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 54 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 9.2.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is un limited. each byte of 8 bits is followed by an acknowledge cycle. ? a slave receiver which is addressed must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be considered). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is shown in figure 45 . 9.2.5 i 2 c-bus controller the pcf8537ah acts as an i 2 c-bus slave receiver. it does not initiate i 2 c-bus transfers or transmit data to an i 2 c-bus master receiver. the only data output from pcf8537ah are the acknowledge signals and the temperatur e readout byte of the selected device. fig 44. system configuration mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig 45. acknowledgement on the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 55 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 9.2.6 input filters to enhance noise immunity in electrically ad verse environments, rc low-pass filters are provided on the sda and scl lines. 9.2.7 i 2 c-bus slave address the device selection depends on the i 2 c-bus slave address. two different i 2 c-bus slave addresses can be used to address the pcf8537ah (see ta b l e 3 1 ). bit 1 of the slave address is defined by connecting the input a0 to either v ss (logic 0) or v dd (logic 1). therefore, two instances of pcf8537ah can be distinguished on the same i 2 c-bus. the least significant bit of the slave address byte is bit r/w (see ta b l e 3 2 ). [1] only used for temperature readout from pcf8537ah (see table 20 on page 15 ). 9.2.8 i 2 c-bus protocol the i 2 c-bus protocol is shown in figure 46 . the sequence is initiated with a start condition (s) from the i 2 c-bus master which is followed by one of the two pcf8537ah slave addresses available. all pcf8537ah?s with the corresponding a0 level acknowledge in parallel to the slave address, but all pcf8537ah with an alternative a0 level ignore the whole i 2 c-bus transfer. after acknowledgement, a co ntrol byte follows (see section 9.1 on page 52 ). table 31. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 011100a0r/w table 32. r/w bit description symbol value description r/w data read or write selection 0 write data 1 read data [1]
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 56 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 the display bytes are stored in the display ram at the address specified by the data pointer. the acknowledgement after each byte is made only by the addressed pcf8537ah. after the last display byte, the i 2 c-bus master issues a stop condition (p). alternatively a start may be issued to restart an i 2 c-bus access. 9.2.9 data read if a temperature readout (byte td[7:0]) is made, the r/w bit must be logic 1 and then the next data byte following is provided by the pcf8537ah as shown in figure 47 . fig 46. i 2 c-bus protocol, write mode examples a) transmit two bytes of ram data 013aaa653 a 0 s01110 0 control byte slave address ram/command byte ram data m s b l s b a a p r/w = 0 s01110 0 01 a a a p ram data a b) transmit two command bytes command s01110 0 10 a a a p command a a c) transmit one command byte and two ram date bytes command s01110 0 10 00 01 a a a p ram data a ram data a a c o r s a 0 a 0 a 0 0 0 0 0 fig 47. i 2 c-bus protocol, read mode 013aaa677 a 0 s01110 1 slave address temperature readout byte m s b l s b a p r/w = 1 a acknowledge from pcf8537ah acknowledge from master 0
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 57 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 9.3 spi-bus interface (pcf8537bh) data transfer to the device is made via a three-line spi-bus (see ta b l e 3 0 ). the spi-bus is reset whenever the chip enable pin ce is inactive. [1] the chip enable must not be wired permanently low. 9.3.1 data transmission the chip enable signal is used to identify t he transmitted data. each data transfer is a byte, with the most signif icant bit (msb) sent first. the transmission is controlled by the active low chip enable signal ce . the first byte transmitted is the subaddress byte. the subaddress byte opens the communication with a read/write bit and a subaddress. the subaddress is used to identify multiple devices on one spi-bus. [1] only used for temperature readout from pcf8537bh (see table 20 on page 15 ). after the subaddress byte, a control byte follows (see section 9.1 on page 52 ). table 33. serial interface pin function description ce chip enable input; active low [1] when high, the interface is reset; scl serial clock input - sdio serial data input output input data is sampled on the rising edge of scl; data is output on the falling edge of scl fig 48. data transfer overview table 34. subaddress byte definition bit symbol binary value description 7r/w data read or write selection 0 write data 1 read data [1] 6 to 5 sa[1:0] 01 subaddress ; other codes will cause the device to ignore data transfer 4 to 0 - - unused 013aaa464 data bus ce subaddress data data data
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 58 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 9.3.2 data read the temperature readout data byte td[7:0] can be read from the pcf8537bh. a readout is initiated by sendin g the subaddress byte with the r/w bit set high. the transmission is controlled by the active low chip enable signal ce . after the last bit of the subaddress byte is transmitted, the pcf8537bh will immediately start to drive the sdio line. it is only nece ssary to read the values once, however since the update of the register is asynchronous to the interface clock, it is recommended to read the register twice and check for a stable value. the readout is terminated by asserting ce . at this time, the sdio bus is released. it is important that the bus is not left floating an d that the microcontroller then takes over driving of the bus. data transfers are terminated by de-asserting ce (set ce to logic 1) fig 49. spi-bus write example examples a) transmit two bytes of display ram data 013aaa656 001 control byte subaddress ram/command byte ram data m s b l s b r/w = 0 001 0 ram data b) transmit two command bytes command 001 10 command c) transmit one command byte and two display ram date bytes 00 c o r s 1 command 001 10 ram data 01 ram data in this example, the multiplex mode is set to 1:8. the transfer is terminated by ce returning to logic 1. after the last bit is transmitted, the state of the sdio line is not important. fig 50. spi-bus write example 013aaa657 command byte multiplex drive mode = 1:8 m[2:0] = 111 unused r/w sa scl sdio ce b7 0 b6 0 b5 1 b4 0 b3 0 b2 0 b1 0 b0 0 b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 1
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 59 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 fig 51. spi-bus read example 013aaa678 ce sdio scl temperature data 11 bcd temperature data 11 bcd r/w unused b7 1 b6 0 b5 1 b4 0 b3 0 b2 0 b1 0 b0 0 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 sa microcontroller driving sdio pcf8537bh driving sdio
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 60 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 10. internal circuitry (1) output resistance, r o , see table 36 on page 62 . fig 52. device protection diagram for pcf8537ah (1) output resistance, r o , see table 36 on page 62 . fig 53. device protection diagram for pcf8537bh a0, reset, t1, t2, clk v dd1 v ss 013aaa659 bp0 to bp5, s0 to s43, bp7/s44, bp6/s45 v lcd v ss t3, v lcd , sda, scl, v dd1 , v dd2 v ss (1) sdio, reset, t1, t2, clk v dd1 v ss 013aaa660 bp0 to bp5, s0 to s43, bp7/s44, bp6/s45 v lcd v ss t3, v lcd , ce, scl, v dd1 , v dd2 v ss (1)
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 61 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 11. limiting values [1] pass level; human body model (hbm), according to ref. 6 ? jesd22-a114 ? . [2] pass level; charged-device model (cdm), according to ref. 7 ? jesd22-c101 ? . [3] pass level; latch-up testing according to ref. 8 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the nxp store and transport requirements (see ref. 10 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. caution static voltages across the liquid crystal display can build up when the lcd supply voltage (v lcd ) is on while the ic supply voltage (v dd ) is off, or vice versa. this may cause unwanted display artifacts. to av oid such artifacts, v lcd and v dd must be applied or removed together. table 35. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd1 supply voltage 1 digital ? 0.5 +6.5 v v dd2 supply voltage 2 analog ? 0.5 +6.5 v i dd1 supply current 1 digital ? 50 +50 ma i dd2 supply current 2 analog ? 50 +50 ma v lcd lcd supply voltage ? 0.5 +10 v i dd(lcd) lcd supply current ? 50 +50 ma v i input voltage on pins clk, ce , sda, scl, a0, sdio, t1, t2 ? 0.5 +6.5 v i i input current ? 10 +10 ma v o output voltage on pins s0 to s45, bp0 to bp7 ? 0.5 +10 v on pins sda, sdio, clk ? 0.5 +6.5 v i o output current ? 10 +10 ma i ss ground supply current ? 50 +50 ma p tot total power dissipation - 400 mw p/out power dissipation per output -100mw v esd electrostatic discharge voltage hbm [1] - ? 4500 v cdm [2] - ? 1500 v i lu latch-up current [3] -200ma t stg storage temperature [4] ? 65 +150 ?c t amb ambient temperature operating device ? 40 +85 ?c
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 62 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 12. static characteristics table 36. static characteristics v dd1 = 1.8 v to 5.5 v; v dd2 = 2.5 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 9.0 v; t amb = ? 40 ? c to +85 ? c; temperature measurement enabled; 1: 8 multiplex drive mode; 1 4 bias; lcd outputs are open circuit; ram is all written with logic 1; inputs at v ss or v dd ; internal clock with ma ximum prescale factor; i 2 c-bus/spi-bus inactive; un less otherwise specified. symbol parameter conditions min typ max unit supplies v dd1 supply voltage 1 logic 1.8 - 5.5 v v dd2 supply voltage 2 analog; v dd2 ? v dd1 charge pump set to 2 ? v dd2 2.5 - 5.5 v charge pump set to 3 ? v dd2 2.5 - 5.5 v v lcd lcd supply voltage v lcd ? v dd2 [1] 2.5 - 9.0 v ? v lcd lcd voltage variation v dd1 =v dd2 =5.0v; v lcd = 6.99 v [2] ? 0.10 - +0.10 v i dd1 supply current 1 digital; display disabled; charge pump off -90200 ? a i dd2 supply current 2 display disabled; charge pump off; external v lcd -0.5- ? a v dd2 =5.5v; charge pump set to 2 ? v dd2 ; internal v lcd =7.0v display disabled - 30 40 ? a display enabled [3] -200- ? a i dd(lcd) lcd supply current external v lcd =7.0v; display enabled; -85- ? a i dd(pd) power-down mode supply current on pin v dd1 -13 ? a i lcd(pd) power-down lcd current - 15 25 ? a t acc temperature accuracy read out temperature error; v dd1 =5.0v t amb = ? 40 ? c to +85 ?c ? 5-+5 ?c t amb =25 ?c ? 3-+3 ?c logic v i input voltage v ss ? 0.5 - v dd + 0.5 v v il low-level input voltage on pins clk and a0 - - 0.3v dd v v ih high-level input voltage on pins clk and a0 0.7v dd -- v v o output voltage ? 0.5 - v dd + 0.5 v v oh high-level output voltage on pin clk 0.8v dd -- v v ol low-level output voltage on pin clk - - 0.2v dd v i oh high-level output current output source current; v oh =4.6v; v dd =5v; on pin clk 1-- ma
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 63 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 [1] when supplying external v lcd it must be v lcd ? v dd2 . also when using the internal charge pump to generate a certain v lcd , vpr[7:0] must be set to a value that the voltage is higher than v dd2 (see section 8.4.2 ). [2] calibrated at testing stage. v lcd temperature compensation is disabled. [3] tested on sample basis. [4] if v dd1 < v por a reset occurs. [5] variation between any 2 backplanes on a given voltage level; static measured. [6] variation between any 2 segments on a gi ven voltage level; static measured. [7] outputs measured one at a time. i ol low-level output current output sink current; v ol =0.4v; v dd =5v; on pin clk 1-- ma v por power-on reset voltage [4] --1.6v i l leakage current v i =v dd or v ss ; on pins clk and a0 ? 1-+1 ? a i 2 c- and spi-bus lines; pins sda, scl and sdio v i input voltage pins sda, scl v ss ? 0.5 - 5.5 v pin sdio v ss ? 0.5 - v dd + 0.5 v v il low-level input voltage pins sda, scl, and sdio - - 0.3v dd v v ih high-level input voltage pins sda, scl, and sdio 0.7v dd -- v v o output voltage pins sda and scl ? 0.5 - 5.5 v sdio ? 0.5 - v dd + 0.5 v i ol low-level output current v ol =0.4v; v dd =5v; on pin sda and sdio 3-- ma i oh high-level output current v oh =4.6v; v dd =5v; on pin sdio 3-- ma i l leakage current v i =v dd or v ss ? 1-+1 ? a lcd outputs ? v o output voltage variation on pins bp0 to bp7 [5] ? 15 - +15 mv on pins s0 to s45 [6] ? 15 - +15 mv r o output resistance v lcd = 7 v; on pins bp0 to bp7 [7] 0.3 0.8 1.5 k ? v lcd = 7 v; on pins s0 to s45 [7] 0.6 1.5 3 k ? table 36. static characteristics ?continued v dd1 = 1.8 v to 5.5 v; v dd2 = 2.5 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 9.0 v; t amb = ? 40 ? c to +85 ? c; temperature measurement enabled; 1: 8 multiplex drive mode; 1 4 bias; lcd outputs are open circuit; ram is all written with logic 1; inputs at v ss or v dd ; internal clock with ma ximum prescale factor; i 2 c-bus/spi-bus inactive; un less otherwise specified. symbol parameter conditions min typ max unit
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 64 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 v lcd = 5 v to 9 v. remark: only valid if the charge pump is driven in a safe range as described in figure 18 and figure 19 . a. v dd =5v v lcd = 5 v to 9 v. remark: only valid if the charge pump is driven in a safe range as described in figure 18 and figure 19 . b. v dd =3v fig 54. lcd voltage variation with respect to temperature 013aaa687 -60 -40 -20 0 20 40 60 80 100 -195 -130 -65 0 65 130 195 temperature (oc) v lcd (mv) 013aaa688 -60 -40 -20 0 20 40 60 80 100 -195 -130 -65 0 65 130 195 temperature (oc) v lcd (mv)
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 65 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 v dd2 = 5.0 v; 1:8 multiplex drive mode; 1 4 bias; temperature measurement enabled; lcd outputs are open circuit; ram all logic 1; inputs at v ss or v dd ; internal clock with max prescale factor; bus active. (1) charge pump on; v dd1 = 5.5 v; charge pump configuration: v lcd =2 ? v dd2 ; vpr[7:0] set to 7.0 v; display enabled. (2) charge pump off; v dd1 = 5.0 v; display disabled. fig 55. typical i dd1 with respect to temperature v dd1 =v dd2 = 5.0 v; 1:8 multiplex drive mode; 1 4 bias; temperature measurement enabled; flat temperature compensation; lcd outputs are open circuit; ram all logic 1; inputs at v ss or v dd ; internal clock with max prescale factor; bus i nactive; charge pump on; charge pump configuration: v lcd =2 ? v dd2 ; vpr[7:0] set to 7.0 v; display enabled. fig 56. typical i dd2 with respect to temperature 013aaa668 -60 -40 -20 0 20 40 60 80 100 100 110 120 130 140 150 160 temperature (oc) i dd1 (a) (1) (2) 013aaa669 -60 -40 -20 0 20 40 60 80 100 100 110 120 130 140 150 160 temperature (oc) i dd2 (a)
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 66 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 v dd1 =v dd2 = 5.0 v; 1:8 multiplex drive mode; 1 4 bias; temperature measurement enabled; flat temperature compensation; lcd outputs are open circuit; ram all logic 1; inputs at v ss or v dd ; internal clock with max prescale factor; bus i nactive; charge pump on; charge pump configuration: v lcd = 7.0 v, external supplied; display enabled. fig 57. typical i dd(lcd) with respect to temperature 013aaa670 -60 -40 -20 0 20 40 60 80 100 80 90 100 110 120 130 140 temperature (oc) i dd(lcd) ( ( (a)
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 67 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 13. dynamic characteristics [1] frequency present on oscclk with def ault display frequency division factor. table 37. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss = 0 v; v lcd = 2.5 v to 9.0 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit f clk(ext) external clock frequency 450 - 14500 hz t clk(h) clock high time external clock source used 33 - - ? s t clk(l) clock low time 33 - - ? s f clk clock frequency on pin clk; see table 17 [1] 7800 9600 11040 hz t w(rst)l low-level reset time 400 - - ns fig 58. driver timing waveforms fig 59. reset timing 013aaa296 clk t clk(h) t clk(l) 1/f clk 0.7 v dd 0.3 v dd 013aaa665 reset t w(rst)l 0.3 v dd
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 68 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 [1] internal calibration made with otp so that the maximum variation is ? 15 % over whole temperature and voltage range. the typical f clk frequency generates a typical frame frequency of 200 hz when the default frequency division factor is used. [2] the typical value is defined at v dd1 =v dd2 = 5.0 v and 30 ? c. [3] all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . [4] t vd;dat = minimum time for valid sda output following scl low. [5] t vd;ack = time for acknowledgement signal from scl low to sda output low. table 38. timing characteristics: i 2 c-bus v dd1 = 1.8 v to 5.5 v; v dd2 = 2.5 v to 5.5 v; v ss = 0 v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit f scl scl clock frequency - - 400 khz t buf bus free time between a stop and start condition 1.3 - - ? s t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t vd;dat data valid time [4] --0.9 ? s t vd;ack data valid acknowledge time [5] --0.9 ? s t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s t f fall time of both sda and scl signals - - 0.3 ? s t r rise time of both sda and scl signals - - 0.3 ? s c b capacitive load for each bus line - - 400 pf t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.6 - - ? s t w(spike) spike pulse width - - 50 ns fig 60. i 2 c-bus timing waveforms scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 013aaa417 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 69 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 table 39. timing characteristics: spi-bus v dd = 1.8 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c. all timing values are valid within the operating supply voltage and temperature range and referenced to v il and v ih with an input voltage swing of v ss to v dd . symbol parameter conditions v dd < 2.7 v v dd ? 2.7 v unit min max min max timing characteristics (see figure 61 ) f clk(scl) scl clock frequency - 2 - 5 mhz t scl scl time 500 - 200 - ns t clk(h) clock high time 200 - 80 - ns t clk(l) clock low time 200 - 80 - ns t r rise time for scl signal - 100 - 100 ns t f fall time for scl signal - 100 - 100 ns t su(ce ) ce set-up time 150 - 80 - ns t h(ce) ce hold time 0 - 0 - ns t rec(ce ) ce recovery time 100 - 100 - ns t su set-up time set-up time for sdi data 35 - 10 - ns t h hold time hold time for sdi data 25 - 15 - ns fig 61. spi-bus timing 013aaa679 b7 b6 b0 sdio scl ce 70 % 30 % t clk(l) t f t h(ce) t rec(ce) t r t h t su t clk(h) t scl t su(ce) b7 b6 b0 sdio b7 b6 t d(r)sdio t dis(sdio) t t(sdio-sdio) microcontroller driving sdio bus pcf8537bh driving sdio bus b0 write example read example
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 70 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 14. package outline fig 62. package outline sot357-1 (tqfp64) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.08 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot357-1 137e10 ms-026 00-01-19 02-03-14 d (1) (1)(1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale tqfp64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm sot357-1
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 71 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 15. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 72 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 16.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 16.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 63 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 4 0 and 41 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 63 . table 40. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 41. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 73 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 63. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 74 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 17. abbreviations table 42. abbreviations acronym description aec automotive electronics council cmos complementary metal oxide semiconductor dc direct current eprom erasable programmable read-only memory hbm human body model i 2 c inter-integrated circuit bus ic integrated circuit lcd liquid crystal display lsb least significant bit msb most significant bit msl moisture sensitivity level mux multiplexer otp one time programmable pcb printed-circuit board por power-on reset rc resistance-capacitance ram random access memory rms root mean square scl serial clock line sda serial data line smd surface mount device spi serial peripheral interface
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 75 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 18. references [1] an10365 ? surface mount reflow soldering description [2] an10853 ? esd and emc sensitivity of ic [3] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [4] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [5] ipc/jedec j-std-020d ? moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices [6] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [7] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [8] jesd78 ? ic latch-up test [9] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [10] nx3-00092 ? nxp store and transport requirements [11] snv-fa-01-02 ? marking formats integrated circuits [12] um10204 ? i 2 c-bus specification and user manual
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 76 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 19. revision history table 43. revision history document id release date data sheet status change notice supersedes pcf8537 v.1 20120531 product data sheet - -
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 77 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 20.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 20.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 78 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 20.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 79 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 22. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3. pin description of pcf8537ah and pcf8537bh . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4. commands of pcf8537 . . . . . . . . . . . . . . . . . .7 table 5. initialize - initialize command bit description . . .8 table 6. otp-refresh - otp-refresh command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 7. oscillator-ctrl - o scillator control command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 8. charge-pump-ctrl - charge pump control command bit description . . . . . . . . . . . . . . . . . .9 table 9. temp-msr-ctrl - temperature measurement control command bit description . . . . . . . . . . . . . . . . .10 table 10. temp-comp - temperature compensation coefficients command . . . . . . . . . . . . . . . . . . .10 table 11. set-vpr - set vpr command bit description . 11 table 12. display-enable - display enable command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 13. set-mux-mode - set multiplex drive mode command bit description . . . . . . . . . . . . . . . . .12 table 14. set-bias-mode - set bias mode command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 15. load-data-pointer - load data pointer command bit description . . . . . . . . . . . . . . . . . . . . . . . . .12 table 16. frame frequency - frame frequency and output clock frequency command bit description . . . .13 table 17. frame frequency values . . . . . . . . . . . . . . . . .13 table 18. bank-select - bank select command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 19. write-ram-data - write ram data command bit description . . . . . . . . . . . . . . . . . . . . . . . . .14 table 20. temp-read - temperature readout command bit description . . . . . . . . . . . . . . . . . . . . . . . . .15 table 21. invmode_ctrl - drive scheme inversion command bit description . . . . . . . . . . . . . . . . .15 table 22. temp-filter - digital temperature filter command bit description . . . . . . . . . . . . . . . . . . . . . . . . .16 table 23. reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 24. selection of display configurations . . . . . . . . . .23 table 25. temperature measurement update rate . . . . . .28 table 26. temperature coefficients. . . . . . . . . . . . . . . . . .30 table 27. calculation of the v lcd offset voltage. . . . . . . .31 table 28. lcd drive modes: su mmary of characteristics .32 table 29. mapping of output pins and corresponding signals with respect to driving mode. . . . . . . . .42 table 30. control byte description . . . . . . . . . . . . . . . . . .52 table 31. i 2 c slave address byte . . . . . . . . . . . . . . . . . . .55 table 32. r/w bit description . . . . . . . . . . . . . . . . . . . . . .55 table 33. serial interface . . . . . . . . . . . . . . . . . . . . . . . . .57 table 34. subaddress byte definition . . . . . . . . . . . . . . . .57 table 35. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .61 table 36. static characteristics . . . . . . . . . . . . . . . . . . . .62 table 37. dynamic characteristics . . . . . . . . . . . . . . . . . .67 table 38. timing characteristics: i 2 c-bus . . . . . . . . . . . .68 table 39. timing characteristics: spi-bus . . . . . . . . . . . .69 table 40. snpb eutectic process (from j-std-020c) . . . 72 table 41. lead-free process (from j-std-020c) . . . . . . 72 table 42. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 43. revision history . . . . . . . . . . . . . . . . . . . . . . . . 76
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 80 of 82 nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 23. figures fig 1. block diagram of pcf8537ah . . . . . . . . . . . . . . . .3 fig 2. block diagram of pcf8537bh . . . . . . . . . . . . . . . .4 fig 3. pin configuration for tqfp64 (pcf8537ah). . . . .5 fig 4. pin configuration for tqfp64 (pcf8537bh). . . . .5 fig 5. recommended start-up sequence when using the internal charge pump and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 fig 6. recommended start-up sequence when using an external supplied v lcd and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 fig 7. recommended start-up sequence when using the internal charge pump and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 fig 8. recommended start-up sequence when using an external supplied v lcd and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 fig 9. recommended power-down sequence for minimum power-down current when using the internal charge pump and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 fig 10. recommended power-down sequence when using an external supplied v lcd and the internal clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 fig 11. recommended power-down sequence when using the internal charge pump and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 fig 12. recommended power-down sequence for minimum power-down current when using an external supplied v lcd and an external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 fig 13. example of displays suitable for pcf8537 . . . . .23 fig 14. typical i 2 c system configuration when using the internal v lcd generation . . . . . . . . . . . . . . . .24 fig 15. typical spi system configuration when using an external v lcd . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 16. v lcd generation including temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .25 fig 17. v lcd programming of pcf8537 (assuming vt[7:0] = 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 fig 18. charge pump driving capability with v dd2 = 3.3 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 fig 19. charge pump driving capability with v dd2 = 5.0 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 fig 20. temperature measurement block with digital temperature filter . . . . . . . . . . . . . . . . . . . . . . . . .29 fig 21. temperature measurement delay during ramping up-down of the environment temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 fig 22. example of segmented temperature coefficients.30 fig 23. electro-optical ch aracteristic: relative transmission curve of the liquid . . . . . . . . . . . . . .33 fig 24. static drive mode waveforms (line inversion mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 fig 25. waveforms for the 1:2 multiplex drive mode with 1 2 bias (line inversion mode) . . . . . . . . . . . .35 fig 26. waveforms for the 1:2 multiplex drive mode with 1 3 bias (line inversion mode) . . . . . . . . . . . . 36 fig 27. waveforms for the 1:4 multiplex drive mode with 1 3 bias (line inversion mode) . . . . . . . . . . . . 37 fig 28. waveforms for 1:6 multiplex drive mode with 1 3 bias (line inversion mode) . . . . . . . . . . . . 38 fig 29. waveforms for 1:6 multiplex drive mode with 1 4 bias (line inversion mode) . . . . . . . . . . . . 39 fig 30. waveforms for 1:8 multiplex drive mode with 1 4 bias (line inversion mode) . . . . . . . . . . . . 40 fig 31. waveforms for 1:8 multiplex drive mode with 1 4 bias (frame inversion mo de) . . . . . . . . . . 41 fig 32. display ram bitmap . . . . . . . . . . . . . . . . . . . . . . 45 fig 33. display ram filling order in static drive mode . . . 47 fig 34. discarded bits at the end of data transmission . . 47 fig 35. display ram filling order in 1:2 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 fig 36. display ram filling order in 1:4 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 fig 37. display ram filling order in 1:6 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 fig 38. display ram filling order in 1:8 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 fig 39. bank selection. . . . . . . . . . . . . . . . . . . . . . . . . . . 50 fig 40. example of the bank-select command with multiplex drive mode 1:4 . . . . . . . . . . . . . . . . . . . 50 fig 41. control byte format . . . . . . . . . . . . . . . . . . . . . . . 52 fig 42. bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 fig 43. definition of start and stop conditions . . . . . 53 fig 44. system configuration. . . . . . . . . . . . . . . . . . . . . . 54 fig 45. acknowledgement on the i 2 c-bus. . . . . . . . . . . . 54 fig 46. i 2 c-bus protocol, write mode. . . . . . . . . . . . . . . . 56 fig 47. i 2 c-bus protocol, read mode . . . . . . . . . . . . . . . . 56 fig 48. data transfer overview . . . . . . . . . . . . . . . . . . . . 57 fig 49. spi-bus write example . . . . . . . . . . . . . . . . . . . . 58 fig 50. spi-bus write example . . . . . . . . . . . . . . . . . . . . 58 fig 51. spi-bus read example. . . . . . . . . . . . . . . . . . . . . 59 fig 52. device protection diagram for pcf8537ah . . . . 60 fig 53. device protection diagram for pcf8537bh . . . . 60 fig 54. lcd voltage variation with respect to temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 fig 55. typical i dd1 with respect to temperature . . . . . . . 65 fig 56. typical i dd2 with respect to temperature . . . . . . . 65 fig 57. typical i dd(lcd) with respect to temperature . . . . 66 fig 58. driver timing waveforms . . . . . . . . . . . . . . . . . . . 67 fig 59. reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 fig 60. i 2 c-bus timing waveforms . . . . . . . . . . . . . . . . . . 68 fig 61. spi-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 69 fig 62. package outline sot357-1 (tqfp64) . . . . . . . . 70 fig 63. temperature profiles for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
pcf8537 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 31 may 2012 81 of 82 continued >> nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 7 8.1 commands of pcf8537 . . . . . . . . . . . . . . . . . . 7 8.1.1 command: initialize . . . . . . . . . . . . . . . . . . . . . 8 8.1.2 command: otp-refresh . . . . . . . . . . . . . . . . . . 8 8.1.3 command: oscillator-ctrl . . . . . . . . . . . . . . . . . 8 8.1.3.1 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1.3.2 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . 9 8.1.3.3 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.1.4 command: charge-pump-ctrl . . . . . . . . . . . . . . 9 8.1.5 command: temp-msr-ctrl . . . . . . . . . . . . . . . . 10 8.1.6 command: temp-comp . . . . . . . . . . . . . . . . . 10 8.1.7 command: set-vpr . . . . . . . . . . . . . . . . . . . . 11 8.1.8 command: display-enable . . . . . . . . . . . . . . . 11 8.1.9 command: set-mux-mode . . . . . . . . . . . . . . 12 8.1.10 command: set-bias-mode . . . . . . . . . . . . . . . 12 8.1.11 command: load-data-pointer. . . . . . . . . . . . . 12 8.1.12 command: frame-frequency . . . . . . . . . . . . . 13 8.1.12.1 timing and frame frequency . . . . . . . . . . . . . . 14 8.1.13 command: bank-select . . . . . . . . . . . . . . . . . 14 8.1.14 command: write-ram-data . . . . . . . . . . . . . . 14 8.1.15 command: temp-read . . . . . . . . . . . . . . . . . . 15 8.1.16 command: invmode_ctrl . . . . . . . . . . . . . . . . 15 8.1.17 command: temp-filter . . . . . . . . . . . . . . . . . . 16 8.2 start-up and shut-down. . . . . . . . . . . . . . . . . . 17 8.2.1 power-on reset (por) . . . . . . . . . . . . . . . . . 17 8.2.2 reset pin function . . . . . . . . . . . . . . . . . . . . 18 8.2.3 recommended start-up sequences . . . . . . . . 18 8.2.4 recommended sequences to enter power-down mode . . . . . . . . . . . . . . . . . . . . . 20 8.3 possible display configurations . . . . . . . . . . . 23 8.4 lcd supply voltage. . . . . . . . . . . . . . . . . . . . . 25 8.4.1 external v lcd supply . . . . . . . . . . . . . . . . . . . 25 8.4.2 internal v lcd generation . . . . . . . . . . . . . . . . . 25 8.4.3 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4.3.1 charge pump configuration . . . . . . . . . . . . . . 26 8.4.3.2 charge pump driving capability . . . . . . . . . . . 26 8.4.4 temperature measur ement and temperature compensation of v lcd . . . . . . . . . . . . . . . . . . 28 8.4.4.1 temperature readout . . . . . . . . . . . . . . . . . . . 28 8.4.4.2 temperature adjustment of the v lcd . . . . . . . 30 8.4.5 lcd voltage selector . . . . . . . . . . . . . . . . . . . 31 8.4.5.1 electro-optical performance . . . . . . . . . . . . . . 33 8.4.6 lcd drive mode waveforms. . . . . . . . . . . . . . 34 8.4.6.1 static drive mode . . . . . . . . . . . . . . . . . . . . . . 34 8.4.6.2 1:2 multiplex drive mode . . . . . . . . . . . . . . . . 35 8.4.6.3 1:4 multiplex drive mode . . . . . . . . . . . . . . . . 37 8.4.6.4 1:6 multiplex drive mode . . . . . . . . . . . . . . . . 38 8.4.6.5 1:8 multiplex drive mode . . . . . . . . . . . . . . . . 40 8.5 backplane and segment outputs . . . . . . . . . . 42 8.5.1 backplane outputs . . . . . . . . . . . . . . . . . . . . . 42 8.5.1.1 1:8 multiplex drive mode . . . . . . . . . . . . . . . . 42 8.5.1.2 1:6 multiplex drive mode . . . . . . . . . . . . . . . . 42 8.5.1.3 1:4 multiplex drive mode . . . . . . . . . . . . . . . . 42 8.5.1.4 1:2 multiplex drive mode . . . . . . . . . . . . . . . . 42 8.5.1.5 static drive mode . . . . . . . . . . . . . . . . . . . . . . 43 8.5.2 segment outputs . . . . . . . . . . . . . . . . . . . . . . 43 8.5.2.1 static, 1:8, 1:4, 1:2 multiplex drive mode . . . . 43 8.5.2.2 1:6 multiplex drive mode . . . . . . . . . . . . . . . . 43 8.6 display controller . . . . . . . . . . . . . . . . . . . . . . 44 8.7 display register . . . . . . . . . . . . . . . . . . . . . . . 44 8.8 display ram . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.8.1 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.8.2 ram filling in static drive mode . . . . . . . . . . . 47 8.8.3 ram filling in 1:2 multiplex drive mode . . . . . 47 8.8.4 ram filling in 1:4 multiplex drive mode . . . . . 48 8.8.5 ram filling in 1:6 multiplex drive mode . . . . . 48 8.8.6 ram filling in 1:8 multiplex drive mode . . . . . 49 8.9 bank selection . . . . . . . . . . . . . . . . . . . . . . . . 50 8.9.1 input bank selection . . . . . . . . . . . . . . . . . . . . 50 8.9.2 output bank selection . . . . . . . . . . . . . . . . . . 51 9 bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 control byte . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 i 2 c-bus interface characteristics (pcf8537ah) . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2.2 start and stop conditions. . . . . . . . . . . . . 53 9.2.3 system configuration . . . . . . . . . . . . . . . . . . . 53 9.2.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.5 i 2 c-bus controller . . . . . . . . . . . . . . . . . . . . . . 54 9.2.6 input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.7 i 2 c-bus slave address . . . . . . . . . . . . . . . . . . 55 9.2.8 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.9 data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3 spi-bus interface (pcf8537bh) . . . . . . . . . . 57 9.3.1 data transmission . . . . . . . . . . . . . . . . . . . . . 57 9.3.2 data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
nxp semiconductors pcf8537 industrial lcd driver for multiplex rates up to 1:8 ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 31 may 2012 document identifier: pcf8537 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 10 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 60 11 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 61 12 static characteristics. . . . . . . . . . . . . . . . . . . . 62 13 dynamic characteristics . . . . . . . . . . . . . . . . . 67 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 70 15 handling information. . . . . . . . . . . . . . . . . . . . 71 16 soldering of smd packages . . . . . . . . . . . . . . 71 16.1 introduction to soldering . . . . . . . . . . . . . . . . . 71 16.2 wave and reflow soldering . . . . . . . . . . . . . . . 71 16.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 72 16.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 72 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 74 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . 76 20 legal information. . . . . . . . . . . . . . . . . . . . . . . 77 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 77 20.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 20.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 20.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 78 21 contact information. . . . . . . . . . . . . . . . . . . . . 78 22 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 23 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 24 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

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